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A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.

Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, and S. Yin. VLSI Circuits, page 1-2. IEEE, (2021)

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Shaojun Lu

Shaojun Tong

Wei Wei

Other publications of authors with the same name

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.Y. Wang, L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, and S. Wei. Sci. China Inf. Sci., 56 (11): 1-20 (2013)Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system.L. Liu, Y. Chen, S. Yin, L. Zhou, H. Yuan, and S. Wei. Sci. China Inf. Sci., 57 (8): 1-14 (2014)Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures.S. Yin, X. Yao, D. Liu, L. Liu, and S. Wei. IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1895-1908 (2016)A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System.M. Zhu, L. Liu, S. Yin, C. Yin, and S. Wei. IEICE Trans. Inf. Syst., 93-D (12): 3202-3210 (2010)Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.Y. Lu, L. Liu, Y. Deng, J. Weng, Z. Li, C. Deng, and S. Wei. DAC, page 71:1-71:6. ACM, (2017)PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC.C. Deng, L. Liu, Y. Liu, S. Yin, and S. Wei. IEEE Trans. Circuits Syst. II Express Briefs, 64-II (5): 540-544 (2017)A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration.S. Liang, S. Yin, L. Liu, Y. Guo, and S. Wei. IEEE Comput. Archit. Lett., 15 (2): 69-72 (2016)A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection.G. Peng, L. Liu, S. Zhou, S. Yin, and S. Wei. IEEE J. Solid State Circuits, 55 (2): 505-519 (2020)Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning.Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, and S. Yin. IEEE J. Solid State Circuits, 57 (10): 3164-3178 (2022)SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning.Y. Wang, Y. Qin, L. Liu, S. Wei, and S. Yin. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (10): 4014-4027 (2022)

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Disambiguation of "Wei, Shaojun"

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A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wei, Shaojun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.