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A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.

Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, and S. Yin. VLSI Circuits, page 1-2. IEEE, (2021)

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Wei Wei

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TPE: A High-Performance Edge-Device Inference with Multi-level Transformational Mechanism.Z. Wang, J. Wei, X. Tang, B. Han, H. He, L. Liu, S. Wei, and S. Yin. AICAS, page 1-5. IEEE, (2023)CPE: An Energy-Efficient Edge-Device Training with Multi-dimensional Compression Mechanism.Z. Wang, J. Wei, B. Han, H. He, L. Liu, S. Wei, and S. Yin. DAC, page 1-6. IEEE, (2023)CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering.R. Guo, Y. Wang, X. Chen, L. Wang, H. Sun, J. Wei, L. Liu, S. Wei, Y. Hu, and S. Yin. A-SSCC, page 1-3. IEEE, (2023)Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow.Y. Qin, Y. Wang, D. Deng, X. Yang, Z. Zhao, Y. Zhou, Y. Fan, J. Wei, T. Chen, L. Liu and 3 other author(s). IEEE J. Solid State Circuits, 59 (10): 3342-3356 (October 2024)A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing.Y. Wang, Y. Qin, D. Deng, J. Wei, Y. Zhou, Y. Fan, T. Chen, H. Sun, L. Liu, S. Wei and 1 other author(s). ISSCC, page 1-3. IEEE, (2022)A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination.Y. Qin, Y. Wang, D. Deng, X. Yang, Z. Zhao, Y. Zhou, Y. Fan, J. Wei, T. Chen, L. Liu and 3 other author(s). A-SSCC, page 1-3. IEEE, (2023)CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering.R. Guo, X. Chen, L. Wang, Y. Wang, H. Sun, J. Wei, H. Han, L. Liu, S. Wei, Y. Hu and 1 other author(s). IEEE J. Solid State Circuits, 59 (10): 3317-3329 (October 2024)Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning.Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, and S. Yin. IEEE J. Solid State Circuits, 57 (10): 3164-3178 (2022)A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, and S. Yin. VLSI Circuits, page 1-2. IEEE, (2021)

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Disambiguation of "Wei, Jingchuan"

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A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.

Please choose a person to relate this publication to

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wei, Jingchuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.

Please choose a person to relate this publication to

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.