%0 Conference Paper %1 conf/isscc/YoshiokaSWKKIFS17 %A Yoshioka, Kentaro %A Sugimoto, Tomohiko %A Waki, Naoya %A Kim, Sinnyoung %A Kurose, Daisuke %A Ishii, Hirotomo %A Furuta, Masanori %A Sai, Akihide %A Itakura, Tetsuro %B ISSCC %D 2017 %I IEEE %K dblp %P 478-479 %T 28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2017.html#YoshiokaSWKKIFS17 %@ 978-1-5090-3758-2

@inproceedings{conf/isscc/YoshiokaSWKKIFS17, added-at = {2022-12-07T00:00:00.000+0100}, author = {Yoshioka, Kentaro and Sugimoto, Tomohiko and Waki, Naoya and Kim, Sinnyoung and Kurose, Daisuke and Ishii, Hirotomo and Furuta, Masanori and Sai, Akihide and Itakura, Tetsuro}, biburl = {https://www.bibsonomy.org/bibtex/25c17b7bbe4a411317708a018080a731d/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2017}, ee = {https://doi.org/10.1109/ISSCC.2017.7870469}, interhash = {bf9b1190389e402e8125580c8158890d}, intrahash = {5c17b7bbe4a411317708a018080a731d}, isbn = {978-1-5090-3758-2}, keywords = {dblp}, pages = {478-479}, publisher = {IEEE}, timestamp = {2024-04-10T11:03:47.000+0200}, title = {28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2017.html#YoshiokaSWKKIFS17}, year = 2017 }