( en | de | ru )

 

Disambiguation of "Itakura, Tetsuro"

Author of the publication

copydeleteadd this publication to your clipboard
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.

, , , , , , , , and . ISSCC, page 478-479. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tetsuro Samata

Uta Itakura

 

Other publications of authors with the same name

A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters., , , , and . CICC, page 501-504. IEEE, (2006)A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching., , , and . IEEE J. Solid State Circuits, 37 (7): 809-816 (2002)A novel quality factor tuning scheme for active-RC filters., , , and . ESSCIRC, page 496-499. IEEE, (2007)A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop., , and . ISSCC, page 98-100. IEEE, (2011)A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (2): 557-560 (2008)A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (2): 411-420 (2009)28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique., , , , , , , , and . ISSCC, page 478-479. IEEE, (2017)26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS., , , , , , and . ISSCC, page 436-437. IEEE, (2016)6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA., , , , , , , , and . ISSCC, page 122-123. IEEE, (2016)19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC., , , , , and . ISSCC, page 336-337. IEEE, (2016)