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Disambiguation of "Furuta, Masanori"

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28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.

, , , , , , , , and . ISSCC, page 478-479. IEEE, (2017)

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Hirokiyo Furuta

 

Other publications of authors with the same name

A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier., , , and . VLSI-DAT, page 1-4. IEEE, (2013)A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues., , and . ISCAS, page 1031-1034. IEEE, (2006)20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication., , , , , , , , , and 10 other author(s). ISSCC, page 348-349. IEEE, (2014)A digitally skew correctable multi-phase clock generator using a master-slave DLL., , , and . ISCAS (1), page 105-108. IEEE, (2003)A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors., , , and . ISCAS, page 357-360. IEEE, (2015)An area-efficient sampling rate converter using negative feedback technique., , , and . ISCAS, page 1922-1925. IEEE, (2008)A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture., , and . IEEE J. Solid State Circuits, 38 (2): 369-373 (2003)All-digital background calibration for time-interleaved ADC using pseudo aliasing signal., , , and . ISCAS, page 1050-1053. IEEE, (2012)Design of Parallel Image Compression Circuits for High-speed CMOS Image Sensors., , , and . Inf. Media Technol., 2 (3): 704-712 (2007)A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC., , , and . ISCAS, page 1151-1154. IEEE, (2014)