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Prophet/Critic Hybrid Branch Prediction., , , , and . ISCA, page 250-263. IEEE Computer Society, (2004)A Minimal Dual-Core Speculative Multi-Threading Architecture., , , and . ICCD, page 360-367. IEEE Computer Society, (2004)Signature Buffer: Bridging Performance Gap between Registers and Caches., , and . HPCA, page 164-175. IEEE Computer Society, (2004)A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications., , , , , , and . ESSCIRC, page 355-358. IEEE, (2005)Microarchitecture of the 80960 high-integration processors., , and . ICCD, page 362-365. IEEE, (1988)Direct load: dependence-linked dataflow resolution of load address and cache coordinate., , , , and . MICRO, page 76-87. ACM/IEEE Computer Society, (2001)Dynamic addressing memory arrays with physical locality., , , , and . MICRO, page 161-170. ACM/IEEE Computer Society, (2002)Coming challenges in microarchitecture and architecture., , , , , and . Proc. IEEE, 89 (3): 325-340 (2001)Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches., , and . ISCA, page 437. ACM, (1992)Scalable Load and Store Processing in Latency-Tolerant Processors., , , , and . IEEE Micro, 26 (1): 30-39 (2006)