Author of the publication

Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries.

M. Ko, G. Kang, K. Kim, J. Lee, S. Koh, T. Kong, S. Kim, S. Lee, M. Choi, J. Shin, G. Cho, and H. Kim. ISSCC, page 204-206. IEEE, (2020)

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Dong-Shin Shin

Jeonghun Shin

Kirche als Weltforum: zum Dialogverständnis in kirchlichen Dokumenten seit dem Zweiten Vatikanischen KonzilJ. Shin. Uni München, (2009)

Hwa-Ja Shin

Jung-Hyu Shin

Hyung-Uk Shin

Other publications of authors with the same name

At-speed logic BIST using a frozen clock testing strategy.J. Shin, X. Yu, E. Rudnick, and M. Abramovici. ITC, page 64-71. IEEE Computer Society, (2001)A 0.65V 1316µm2Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS.J. Park, J. Kim, K. Kim, J. Yang, M. Choi, and J. Shin. ISSCC, page 220-222. IEEE, (2022)Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor.J. Jeong, H. Kim, J. Park, J. Shin, and J. Jeong. IEEE Access, (2023)A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization.S. Choi, H. Son, J. Shin, S. Lee, B. Kim, H. Park, and J. Sim. IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (2): 276-287 (2016)22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.S. Lee, K. Seong, J. Shin, H. Kim, J. Jeong, S. Yi, J. Kim, E. Kim, S. Jung, S. Hwang and 6 other author(s). ISSCC, page 338-340. IEEE, (2020)6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier.B. Yoo, D. Lim, H. Pang, J. Lee, S. Baek, N. Kim, D. Choi, Y. Choi, H. Yang, T. Yoon and 9 other author(s). ISSCC, page 122-124. IEEE, (2020)An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application.K. Lee, J. Park, Y. Park, B. Koo, S. Do, W. Lim, S. Lee, H. Shin, E. Oh, Y. Cho and 2 other author(s). VLSI Technology and Circuits, page 142-143. IEEE, (2022)A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.K. Chae, J. Song, Y. Choi, J. Park, B. Koo, J. Oh, S. Yi, W. Lee, D. Kim, K. Kang and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 231-242 (January 2024)A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA.J. Shin, I. Seo, J. Kim, S. Yang, C. Kim, J. Park, H. Kim, M. Kwak, and G. Hong. CICC, page 409-412. IEEE, (2006)A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.K. Moon, D. Oh, Y. Park, K. Lee, S. Park, S. Lee, H. Hwang, H. Shin, Y. Cho, M. Choi and 1 other author(s). VLSI Technology and Circuits, page 172-173. IEEE, (2022)

BibSonomy

Disambiguation of "Shin, Jongshin"