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Disambiguation of "Kim, Eunsu"

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22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.

, , , , , , , , , , , , , , , and . ISSCC, page 338-340. IEEE, (2020)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-Koreanisch. Uni Heidelberg, (2008)

Baeckpyeng Kim

Kison Kim

Wonchan Kim

Sangho Kim

 

Other publications of authors with the same name

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique., , , , , , , , , and 6 other author(s). ISSCC, page 338-340. IEEE, (2020)The Generative AI Paradox in Evaluation: "What It Can Solve, It May Not Evaluate"., , , and . EACL (Student Research Workshop), page 248-257. Association for Computational Linguistics, (2024)Optimal Trajectory Generation for Walking Up and Down a Staircase with a Biped Robot Using Genetic Algorithm (GA)., , and . FIRA, volume 5744 of Lecture Notes in Computer Science, page 103-111. Springer, (2009)BLEnD: A Benchmark for LLMs on Everyday Knowledge in Diverse Cultures and Languages., , , , , , , , , and 12 other author(s). CoRR, (2024)A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 231-242 (January 2024)23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller., , , , , , , , , and 7 other author(s). ISSCC, page 398-399. IEEE, (2017)Generation of optimal trajectories for ascending and descending a stair of a humanoid based on uDEAS., , and . FUZZ-IEEE, page 660-665. IEEE, (2009)Digital Pattern Search and Its Hybridization with Genetic Algorithms for Bound Constrained Global Optimization., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (2): 481-492 (2009)A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection., , , , , , , , , and 8 other author(s). ISSCC, page 406-407. IEEE, (2023)13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets., , , , , , , , , and 7 other author(s). ISSCC, page 250-252. IEEE, (2024)