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Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM., , , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 364-372 (2016)A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure., , , , , и . ISCAS (1), стр. 73-76. IEEE, (2005)A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , и . SoCC, стр. 143-147. IEEE, (2012)A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 156-157. IEEE, (2013)FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs., , , , , и . ESSCIRC, стр. 265-268. IEEE, (2016)28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique., , , , , , , , , и 1 other автор(ы). IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 575-584 (2014)A low power SRAM using auto-backgate-controlled MT-CMOS., , , , , , , и . ISLPED, стр. 293-298. ACM, (1998)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , и . ICCAD, стр. 398-405. IEEE Computer Society, (2005)The LSI implementation of a memory based field programmable device for MCU peripherals., , , , , , и . DDECS, стр. 183-188. IEEE Computer Society, (2014)Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory., , , , , , , , , и 47 other автор(ы). IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 253-280 (2019)