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Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells., , , , , , , , , и 4 other автор(ы). J. Parallel Distributed Comput., 74 (6): 2484-2496 (2014)A Discussion on Test Pattern Generation for FPGA - Implemented Circuits., , , , и . J. Electron. Test., 17 (3-4): 283-290 (2001)DCG-FGT transistor: Retention study of Floating Gate charge., , , , , и . MWSCAS, стр. 825-827. IEEE, (2013)Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization., , , , , , , , , и 4 other автор(ы). IRPS, стр. 1-6. IEEE, (2021)A Self-referenced and regulated sensing solution for PCM with OTS selector., , , , , , и . VLSI-SoC, стр. 1-6. IEEE, (2021)1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing., , , , , , , , , и 10 other автор(ы). IMW, стр. 1-4. IEEE, (2022)Minimizing the Number of Test Configurations for Different FPGA Families., , , и . Asian Test Symposium, стр. 363-368. IEEE Computer Society, (1999)Metal filling impact on standard cells: definition of the metal fill corner concept., , , , и . SBCCI, стр. 16-21. ACM, (2008)A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology., , и . DATE, стр. 1404-1405. IEEE Computer Society, (2004)Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing., , , , , , , и . DATE, стр. 1187-1192. IEEE, (2020)