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Disambiguation of "Cerqueira, Joao Pedro"

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1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision.

, , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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João Pedro Quintais

João Pedro Gomes Moreira Pêgo

João Pedro Leitão Cruz Morais

Gil dos Santos Guerreiro João

Benno Pedrotti

 

Other publications of authors with the same name

Pipelining a triggered processing element., , , and . MICRO, page 96-108. ACM, (2017)A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies., , , , and . MWSCAS, page 1049-1052. IEEE, (2019)A 450mV timing-margin-free waveform sorter based on body swapping error correction., , and . VLSI Circuits, page 1-2. IEEE, (2016)A 1μW voice activity detector using analog feature extraction and digital deep neural network., , , , , and . ISSCC, page 346-348. IEEE, (2018)Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing., , , , , and . VLSI Circuits, page 54-. IEEE, (2019)A 0.17-mm2 3.19-nJ/transform 256-point fast fourier transform core based on spatiotemporally fine-grained active leakage suppression., and . ESSCIRC, page 47-50. IEEE, (2017)Near-Vt adaptive microprocessor and power-management-unit system based on direct error regulation., , and . ESSCIRC, page 163-166. IEEE, (2017)Master of none acceleration: a comparison of accelerator architectures for analytical query processing., , , , , , and . ISCA, page 762-773. ACM, (2019)Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device., , , , , , , , and . A-SSCC, page 1-4. IEEE, (2020)Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design.. Columbia University, USA, (2019)