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A fast transistor-chaining algorithm for CMOS cell layout.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (7): 781-786 (1990)

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An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (3): 410-424 (1993)A Hierarchical Test Scheme for System-On-Chip Designs., , , , , , , , and . DATE, page 486-490. IEEE Computer Society, (2002)An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation., , , and . DAC, page 481-486. ACM, (1991)A fast transistor-chaining algorithm for CMOS cell layout., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (7): 781-786 (1990)Channel density reduction by routing over the cells., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (8): 1067-1071 (1991)LiB: A Cell Layout Generator., , , and . DAC, page 474-479. IEEE Computer Society Press, (1990)An optimal transistor-chaining algorithm for CMOS cell layout., , , and . ICCAD, page 344-347. IEEE Computer Society, (1989)