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In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization.

, , , and . IOLTS, page 96-99. IEEE, (2017)

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3D technologies for reconfigurable architectures., , , and . ReCoSoC, page 1-2. IEEE, (2014)A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool., , , , , , , , , and 6 other author(s). DATE, page 1192-1196. ACM, (2015)M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC., , , , , , and . DATE, page 1740-1745. IEEE, (2020)From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges., , , , , , , , , and 2 other author(s). ISPD, page 127. ACM, (2015)Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges., , , , , , and . ICECS, page 157-160. IEEE, (2018)Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations., , , , , , and . 3DIC, page 1-5. IEEE, (2019)An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits., , , and . ISVLSI, page 350-355. IEEE Computer Society, (2015)From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose., , , , , , , , and . 3DIC, page 1-5. IEEE, (2016)Intermediate BEOL process influence on power and performance for 3DVLSI., , , , , , , and . 3DIC, page TS1.3.1-TS1.3.5. IEEE, (2015)16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors., , , , , , , , , and 20 other author(s). IMW, page 1-4. IEEE, (2021)