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Disambiguation of "Ryckaert, Julien"

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Device Scaling roadmap and its implications for Logic and Analog platform.

, , , , , , and . BCICTS, page 1-8. IEEE, (2020)

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Julien Köhrle

Julien Ndinga

Julien Bonnamour

Julien Mouysset

Julien Béthune

 

Other publications of authors with the same name

A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 44 (12): 3486-3498 (2009)A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS., , , and . ESSCIRC, page 484-487. IEEE, (2007)PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 429-430. IEEE, (2022)Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)., , , , , , , , , and 6 other author(s). IRPS, page 1-7. IEEE, (2023)Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Impact of interconnects enhancement on SRAM design beyond 5nm technology node., , , and . ISCAS, page 1-5. IEEE, (2023)Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter., , , , , , , , , and 1 other author(s). OFC/NFOEC, page 1-3. IEEE, (2013)Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications., , , , , , and . ISCAS, page 1-5. IEEE, (2023)Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue.. ISPD, page 89. ACM, (2016)