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Disambiguation of "Chauhan, Yogesh Singh"

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A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling.

, , , , , and . VLSI Design, page 177-182. IEEE Computer Society, (2007)

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Dhirendar Chauhan

Sangeeta Chauhan

Yogesh Rathi

Yogesh Bhargava

Anuradha Chauhan

 

Other publications of authors with the same name

FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator., , , , , and . IEEE Trans. Emerg. Top. Comput., 11 (2): 541-547 (April 2023)Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D Integration., , and . ICCAD, page 1-6. IEEE, (2023)Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes., , , and . DRC, page 1-2. IEEE, (2022)Self-Heating characterization and modeling of 5nm technology node FinFETs., , , , and . DRC, page 1-2. IEEE, (2022)A width-scalable SPICE compact model for GaN HEMTs including self-heating effect., , , , , and . DRC, page 1-2. IEEE, (2022)Compact Modeling of Suspended Gate FET., , , , , and . VLSI Design, page 119-124. IEEE Computer Society, (2008)NCFET-Aware Voltage Scaling., , , , , and . ISLPED, page 1-6. IEEE, (2019)On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth Analysis from Transistors to Full Processor., , , and . IRPS, page 1-6. IEEE, (2024)Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores., , , , , and . DAC, page 41. ACM, (2019)BSIM - Industry standard compact MOSFET models., , , , , , , and . ESSCIRC, page 30-33. IEEE, (2012)