Author of the publication

High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection.

, , , , and . CANDAR, page 351-357. IEEE Computer Society, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Circuit Technique for VLSI Design of a Video Codec., , and . ICC (1), page 250-255. Elsevier, (1984)Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration., and . GI Jahrestagung (1), volume P-67 of LNI, page 458. GI, (2005)Instruction merging to increase parallelism in VLIW architectures., , , , and . SoC, page 143-146. IEEE, (2009)A 1.3-GOPS parallel DSP for high-performance image-processing applications., , , , , and . IEEE J. Solid State Circuits, 35 (7): 946-952 (2000)VLSI components for a 560-Mbit/s HDTV codec., , , and . VCIP, volume 1360 of SPIE Proceedings, SPIE, (1990)A flexible, fully configurable architecture for MPEG-2 video encoding., , , and . ICECS, page 1063-1066. IEEE, (2002)Design of a development system for multimedia applications based on a single chip multiprocessor array., , , and . ICECS, page 1151-1154. IEEE, (1996)Multiprocessor performance for real-time processing of video coding applications., , and . IEEE Trans. Circuits Syst. Video Techn., 2 (2): 221-230 (1992)Experimental violation of the Start-Stop-Approximation using a Holistic Rail-based UWB FMCW-SAR System, , , and . EUSAR 2016: 11th European Conference on Synthetic Aperture Radar, Proceedings of, page 1--4. VDE VERLAG GmbH, (2016)Design of a DPCM codec for VLSI realization in CMOS technology.. Proc. IEEE, 73 (4): 592-598 (1985)