( en | de | ru )

 

Disambiguation of "Ventroux, Nicolas"

Author of the publication

copydeleteadd this publication to your clipboard
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks.

, , , , , , , , and . DATE, page 1039-1044. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nicolas Jeanvoine

Plasma-material interaction and electrode degradation in high voltage ignition discharges. Uni Saarbrücken, (2009)

Lothar Nicolas

Nicólás Penzo

Nicolas Swart

Nicolas Katsarakis

 

Other publications of authors with the same name

Energy-Efficient Use of an Embedded Heterogeneous SoC for the Inference of CNNs., , , and . DSD, page 30-38. IEEE, (2023)Fast Virtual Prototyping of Cyber-Physical Systems using SystemC and FMI: ADAS Use Case., , , , , and . RSP, page 43-49. ACM, (2019)SESAM: An MPSoC Simulation Environment for Dynamic Application Processing., , , , , , and . CIT, page 1880-1886. IEEE Computer Society, (2010)Relation between HCI-induced performance degradation and applications in a RISC processor., , , and . IOLTS, page 67-72. IEEE Computer Society, (2012)Stereovision-based 3D obstacle detection for automotive safety driving assistance., , , , and . ITSC, page 1-6. IEEE, (2009)Rapid prototyping for an optimized MPEG-4 decoder implementation over a parallel heterogenous architecture., , , and . ICASSP (2), page 433-436. IEEE, (2003)Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations., , , and . ICSAMOS, page 250-257. IEEE, (2014)A Low Complex Scheduling Algorithm for Multi-processor System-on-Chip., , and . Parallel and Distributed Computing and Networks, page 540-545. IASTED/ACTA Press, (2005)A new parallel SystemC kernel leveraging manycore architectures., and . DATE, page 487-492. IEEE, (2016)Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study., , , and . DSD, page 390-397. IEEE Computer Society, (2009)