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A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators.

, , , and . IEEE J. Solid State Circuits, 54 (5): 1455-1467 (2019)

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Incremental Sturdy-MASH Sigma-Delta Modulator with Reduced Sensitivity to DAC Mismatch., , , and . ISCAS, page 1-5. IEEE, (2019)A 40 kS/sCalibration-Free Incremental △Σ ADC Achieving 104 dB DR and 105.7 dB SFDR., , , , and . ESSCIRC, page 401-404. IEEE, (2023)On the Optimization of DT Incremental Sigma-Delta Modulators in Combination with CoI Reconstruction Filters., , and . NGCAS, page 82-85. IEEE, (2018)An Automated Design Environment for CT Incremental Sigma-Delta ADCs., , and . ICECS, page 1-4. IEEE, (2020)A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta-Sigma Modulator With Differentially Reset FIR Feedback., , , and . ESSCIRC, page 87-90. IEEE, (2019)A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction., , and . ISSCC, page 236-238. IEEE, (2018)Performance Evaluation of Incremental Sigma-Delta ADCs Based on their NTF., , and . IEEE Trans. Circuits Syst., 67-II (12): 2813-2817 (2020)On the Signal Filtering Property of CT Incremental Sigma-Delta ADCs., , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (11): 1780-1784 (2019)A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators., , , and . IEEE J. Solid State Circuits, 54 (5): 1455-1467 (2019)FIR DACs in CT Incremental Delta-Sigma Modulators., , , , and . ISCAS, page 1-5. IEEE, (2020)