Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units., , , and . IEEE Trans. Computers, 55 (11): 1449-1457 (2006)Fault tolerant FPGA processor based on runtime reconfigurable modules., and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)Functional Self-Testing for Bus-Based Symmetric Multiprocessors., , , and . DATE, page 1304-1309. ACM, (2008)Deterministic software-based self-testing of embedded processor cores., , , , and . DATE, page 92-96. IEEE Computer Society, (2001)An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers., , , and . VTS, page 252-259. IEEE Computer Society, (1999)A scrubbing scheduling approach for reliable FPGA multicore processors with real-time constraints., and . DFT, page 1-4. IEEE Computer Society, (2017)An Effective BIST Scheme for Arithmetic Logic Units., , , and . ITC, page 868-877. IEEE Computer Society, (1997)Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs., , , , and . DFT, page 1-6. IEEE, (2021)An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm., , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 166-177. Springer, (2018)Online error detection in multiprocessor chips: A test scheduling study., , , , and . IOLTS, page 169-172. IEEE, (2013)