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Disambiguation of "Yu, Shuangming"

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A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips.

, , , , , , , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (2): 740-753 (February 2024)

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Yu-Ting Yu

Yu-Yu Su

Sze-Man Yu

Metal complexes with enolatoimine ligands for controlled olefin polymerizations. Uni Konstanz, (2009)

Yu Ding

Yu Gu

 

Other publications of authors with the same name

Efficient Reservoir Encoding Method for Near-Sensor Classification with Rate-Coding Based Spiking Convolutional Neural Networks., , , , and . ISNN (2), volume 11555 of Lecture Notes in Computer Science, page 242-251. Springer, (2019)A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications., , , , , , , , and . ICTA, page 94-95. IEEE, (2020)MorphBungee: A 65nm 7.2mm2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning., , , , , , , , , and 1 other author(s). A-SSCC, page 1-3. IEEE, (2023)MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks., , , , , , , , , and 1 other author(s). BioCAS, page 255-259. IEEE, (2022)A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 71 (2): 740-753 (February 2024)A 128×128 15µm-Pitch DROIC with Pixel-Level 14-Bit ADC., , , , , , , , and . ICTA, page 1-2. IEEE, (2023)A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE., , , , , , , , , and 1 other author(s). ESSCIRC, page 177-180. IEEE, (2023)Floorplanning and Power/Ground Network Design for A Programmable Vision Chip., , , , , , , and . ICTA, page 184-185. IEEE, (2022)A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper)., , , , , , and . ICTA, page 141-142. IEEE, (2020)A High-Speed Parallel FPGA Implementation of Harris Corner Detection., , , , , , and . ICTA, page 71-72. IEEE, (2020)