( en | de | ru )

 

Disambiguation of "Takashima, Daisaburo"

Author of the publication

copydeleteadd this publication to your clipboard
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.

, , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 46 (9): 2171-2179 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Akira Takashima

Makoto Takashima

 

Other publications of authors with the same name

A 7T-SRAM with data-write technique by capacitive coupling., , , , and . A-SSCC, page 1-4. IEEE, (2015)A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM., , , , , , , , , and 9 other author(s). ISSCC, page 262-263. IEEE, (2010)An embedded DRAM technology for high-performance NAND flash memories., , , , , and . ISSCC, page 504-505. IEEE, (2011)A 7T-SRAM With Data-Write Technique by Capacitive Coupling., , , , and . IEEE J. Solid State Circuits, 54 (2): 596-605 (2019)Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee., and . ISSCC, page 36-37. IEEE, (2012)A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode., , , , , , , , , and 5 other author(s). ISSCC, page 459-466. IEEE, (2006)Future system and memory architectures: Transformations by technology and applications., , and . ISSCC, page 530. IEEE, (2011)An Embedded DRAM Technology for High-Performance NAND Flash Memories., , , , , and . IEEE J. Solid State Circuits, 47 (2): 536-546 (2012)A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (9): 2171-2179 (2011)A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1745-1752 (2010)