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Disambiguation of "Shiratake, Shinichiro"

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A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode.

, , , , , , , , , , , , , , and . ISSCC, page 459-466. IEEE, (2006)

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Shinichiro Nishizawa

Shinichiro Matsunaga

Shinichiro Kotsuka

 

Other publications of authors with the same name

Session 24 Overview: Advanced Embedded Memories Memory Subcommittee., , and . ISSCC, page 332-333. IEEE, (2021)A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode., , , , , , , , , and 5 other author(s). ISSCC, page 459-466. IEEE, (2006)Session 30 overview: Emerging memories: Memory and technology directions subcommittees., , , and . ISSCC, page 476-477. IEEE, (2018)A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1745-1752 (2010)A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes., , , , , , , , , and 23 other author(s). ISSCC, page 464-465. IEEE, (2009)SE1: What Technologies Will Shape the Future of Computing?, , , , , , , , , and . ISSCC, page 537-538. IEEE, (2021)A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (9): 2171-2179 (2011)F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems., , , , , and . ISSCC, page 506-508. IEEE, (2017)Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems., , , , , , and . ASP-DAC, page 533-540. IEEE, (2006)Session 30 Overview: Non-Volatile Memories Memory Subcommittee., , and . ISSCC, page 420-421. IEEE, (2021)