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Disambiguation of "Zatt, Bruno"

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A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization.

, , , , , and . ISVLSI, page 73-78. IEEE, (2021)

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Fritz Zattler

Peter Zattler

Bernd Zattler

Jürgen Zattler

Michaela Zattler

 

Other publications of authors with the same name

A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder., , , and . SBCCI, page 10:1-10:6. ACM, (2015)Sample adaptive offset filter hardware design for HEVC encoder., , , , and . VCIP, page 299-302. IEEE, (2014)Configurable hardware design for the HEVC-based Adaptive Loop Filter., , , , and . LASCAS, page 1-4. IEEE, (2014)Speedup-aware history-based tiling algorithm for the HEVC standard., , , and . ICIP, page 824-828. IEEE, (2016)AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design., , , , , , , and . IEEE Open J. Circuits Syst., (2021)High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation., , , , , and . ICIP, page 2680-2684. IEEE, (2023)Hardware design of DC/CFL intra-prediction decoder for the AV1 codec., , , and . SBCCI, page 16. ACM, (2019)Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation., , , , , and . ISCAS, page 1-5. IEEE, (2021)Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders., , , , , and . ISCAS, page 1925-1928. IEEE, (2014)Speedup evaluation of HEVC parallel video coding using Tiles., , , and . J. Real Time Image Process., 17 (5): 1469-1486 (2020)