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Customized SRAM design for low power video code applications., , , and . ISOCC, page 79-80. IEEE, (2016)A low power reconfigurable DCT architecture to trade off image quality for computational complexity., and . ICASSP (5), page 17-20. IEEE, (2004)Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme., , and . ISCAS, page 1-4. IEEE, (2019)High performance and low power FIR filter design based on sharing multiplication., , , , , and . ISLPED, page 295-300. ACM, (2002)Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers., , , and . IEEE Access, (2020)Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 787-793 (2010)A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption., and . J. Signal Process. Syst., 53 (3): 399-410 (2008)Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling., , , and . IET Circuits Devices Syst., 4 (6): 469-478 (2010)Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells., and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1622-1626 (2022)Key Length Reconfigurable ARIA Hardware with S-box Optimization., , and . ICEIC, page 1-3. IEEE, (2021)