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Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules, и . Journal of Micro/Nanolithography, MEMS, and MOEMS, 17 (01): 1 (января 2018)Design issues in heterogeneous 3D/2.5D integration., , , , , и . ASP-DAC, стр. 403-410. IEEE, (2013)Reducing Preemptions and Migrations in Real-Time Multiprocessor Scheduling Algorithms by Releasing the Fairness., , , и . RTCSA (1), стр. 15-24. IEEE Computer Society, (2011)IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options., , , , , и . ICCAD, стр. 89-94. IEEE, (2017)Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs., , , , , , и . ISLPED, стр. 76-81. ACM, (2016)Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs., , , , , , , и . ISLPED, стр. 1-6. IEEE, (2021)Techniques Optimizing the Number of Processors to Schedule Multi-threaded Tasks., , , и . ECRTS, стр. 321-330. IEEE Computer Society, (2012)Template architectures for highly scalable, many-core Heterogeneous SoC: Could-of-Chips., , и . ReCoSoC, стр. 1-7. IEEE, (2018)Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm., , , , , и . PDP, стр. 184-191. IEEE Computer Society, (2016)Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management., , , , и . SAMOS, том 5657 из Lecture Notes in Computer Science, стр. 88-97. Springer, (2009)