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Significance-Driven Logic Compression for Energy-Efficient Multiplier Design.

, , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)

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Significance-Driven Logic Compression for Energy-Efficient Multiplier Design., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)Step Persistence in the Design of GALS Systems., , , , and . Petri Nets, volume 7927 of Lecture Notes in Computer Science, page 190-209. Springer, (2013)Registers for Phase Difference Based Logic., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (6): 720-724 (2007)An Excitation Time Model for General-purpose Memristance Tuning Circuit., , , and . ISCAS, page 1-5. IEEE, (2018)Toward Designing Thermally-Aware Memristance Decoder., , , , and . ISCAS, page 1. IEEE, (2020)Online Testing by Protocol Decomposition., , , and . IOLTS, page 263-268. IEEE Computer Society, (2006)Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited., , , , and . DAC, page 36:1-36:6. ACM, (2017)Wireless data and power transfer of an optogenetic implantable visual cortex stimulator., , , , and . EMBC, page 8006-8009. IEEE, (2015)Self-timed, minimum latency circuits for the internet of things., , , and . Integr., (2019)Low-Latency Contro Structures with Slack., , and . ASYNC, page 164-173. IEEE Computer Society, (2003)