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Significance-Driven Logic Compression for Energy-Efficient Multiplier Design.

, , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)

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Signal Graphs: From Self-Timed to Timed Ones., and . PNPM, page 199-206. IEEE Computer Society, (1985)Analyzing Semantics of Concurrent Hardware Specifications., and . ICPP (3), page 211-218. Pennsylvania State University Press, (1989)0-271-00686-2.Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis., , , , and . DAC, page 63-66. ACM Press, (1996)Synthesis of Speed-Independent Circuits from STG-Unfolding Segment., , , , and . DAC, page 16-21. ACM Press, (1997)Low Latency Synchronization Through Speculation., and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 278-288. Springer, (2004)Global interconnections in FPGAs: modeling and performance analysis., , , , , and . SLIP, page 51-58. ACM, (2008)Hardware and Petri Nets: Application to Asynchronous Circuit Design., , , , and . ICATPN, volume 1825 of Lecture Notes in Computer Science, page 1-15. Springer, (2000)Evaluation of energy-recovering interconnects for low-power 3D stacked ICs., , , and . 3DIC, page 1-5. IEEE, (2009)Modelling and verification of an atomic action protocol implemented in Ada., , , , , , and . Comput. Syst. Sci. Eng., 16 (3): 173-182 (2001)Improving the Security of Dual-Rail Circuits., , , and . CHES, volume 3156 of Lecture Notes in Computer Science, page 282-297. Springer, (2004)