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Disambiguation of "Sin, Sai-Weng"

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A 12V-lnput 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter.

, , , , , , and . ISSCC, page 200-201. IEEE, (2023)

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Sai Li

Sai Zhang

Sai Zhang

Sai Qian

Sin Wong

 

Other publications of authors with the same name

A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators., , , , , and . APCCAS, page 1011-1014. IEEE, (2010)A process- and temperature- insensitive current-controlled delay generator for sampled-data systems., , , , , and . APCCAS, page 1192-1195. IEEE, (2008)A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC., , , , , and . ISCAS, page 551-555. IEEE, (2022)A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction., , , , , and . ESSCIRC, page 169-172. IEEE, (2016)An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications., , , , , , and . ICECS, page 878-881. IEEE, (2010)A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators., , , , , and . ICECS, page 547-550. IEEE, (2010)Hybrid loopfilter sigma-delta modulator with NTF zero compensation., , , and . ISOCC, page 76-79. IEEE, (2011)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC., , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2763-2772 (2012)An FPGA-Based Self-Reconfigurable Arc Fault Detection System for Smart Meters., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (10): 4133-4137 (2022)Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (4): 537-547 (2015)