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A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.

Y. Jiang, K. Wong, C. Cai, S. Sin, S. U, and R. Martins. APCCAS, page 1011-1014. IEEE, (2010)

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Peter Seng

Stefan Seng

Katja Seng

Daniel Seng

Katharina Seng

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A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing.L. Qi, S. Sin, S. U, F. Maloberti, and R. Martins. IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2641-2654 (2017)A frequency up-conversion and two-step channel selection embedded CMOS D/A interface.K. Ieong, C. Fok, P. Mak, S. U., and R. Martins. ISCAS (1), page 392-395. IEEE, (2005)New impulse sampled IIR switched-capacitor interpolators.S. U., R. Martins, and J. Franca. ICECS, page 203-206. IEEE, (1996)An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H.S. Sin, L. Ding, Y. Zhu, H. Wei, C. Chan, U. Chio, S. U, R. Martins, and F. Maloberti. ESSCIRC, page 218-221. IEEE, (2010)A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits.S. Sin, S. U., and R. Martins. ISCAS, IEEE, (2006)A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations.Y. Zhu, C. Chan, S. U, and R. Martins. IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 354-363 (2017)A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction.S. U, R. Martins, and J. Franca. ISCAS, page 177-180. IEEE, (2000)A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC.Y. Zhu, C. Chan, S. Sin, S. U, and R. Martins. VLSIC, page 90-91. IEEE, (2012)Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators.D. Feng, F. Maloberti, S. Sin, S. U, and R. Martins. ISCAS, page 1348-1351. IEEE, (2014)A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS.B. Wang, S. Sin, S. U, F. Maloberti, and R. Martins. A-SSCC, page 117-120. IEEE, (2019)

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Disambiguation of "U, Seng-Pan"

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A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.

Please choose a person to relate this publication to

Peter Seng

Stefan Seng

Katja Seng

Daniel Seng

Katharina Seng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "U, Seng-Pan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.

Please choose a person to relate this publication to

Peter Seng

Stefan Seng

Katja Seng

Daniel Seng

Katharina Seng

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.