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An integrated hardware-software cosimulation environment with automated interface generation.

, , , and . RSP, page 66-71. IEEE Computer Society, (1996)

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Design and Optimization of Multiple-Mesh Clock Network., , and . VLSI-SoC (Selected Papers), volume 464 of IFIP Advances in Information and Communication Technology, page 39-57. Springer, (2014)Clock Gating Synthesis of Pulsed-Latch Circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (7): 1019-1030 (2012)Pulsed-Latch Aware Placement for Timing-Integrity Optimization., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1856-1869 (2011)Prosocial Activists in SNS: The Impact of Isomorphism and Social Presence on Prosocial Behaviors., , and . Int. J. Hum. Comput. Interact., 31 (12): 939-958 (2015)μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications., , and . IEEE Trans. Multim., 7 (1): 67-74 (2005)Schedulability-driven performance analysis of multiple mode embedded real-time systems., , and . DAC, page 495-500. ACM, (2000)Optimization of Machine Learning Guided Optical Proximity Correction., , and . MWSCAS, page 921-924. IEEE, (2018)Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation., , and . ASP-DAC, page 629-634. IEEE, (2008)Automatic insertion of airgap with design rule constraints., and . ASP-DAC, page 381-386. IEEE, (2018)Redundant Via insertion in SADP process with cut merging and optimization., , and . VLSI-SoC, page 1-6. IEEE, (2017)