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Disambiguation of "Chen, Liang-Gee"

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Mapping Scalable Video Coding decoder on multi-core stream processors.

, , , , and . PCS, page 1-4. IEEE, (2009)

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Liang Chen

Liang Chen

Liang Chen

Liang-chi Chen

Yen-liang Chen

 

Other publications of authors with the same name

A bit-level pipelined VLSI architecture for the running order algorithm., , and . IEEE Trans. Signal Process., 45 (8): 2140-2144 (1997)Analysis and Design of On-sensor ECG Processors for Realtime Detection of Cardiac Anomalies Including VF, VT, and PVC., , , , , , , and . J. Signal Process. Syst., 65 (2): 275-285 (2011)Memory efficient architecture for belief propagation based disparity estimation., , , and . ISCAS, page 2521-2524. IEEE, (2015)Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture., , and . ISCAS (2), page 273-276. IEEE, (2004)System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint., , , , , and . ISCAS, page 1001-1004. IEEE, (2007)Low-cost hardware architecture design for 3D warping engine in multiview video applications., , and . ISCAS, page 2964-2967. IEEE, (2010)The Chip Design of A 32-b Logarithmic Number System., , and . ISCAS, page 167-170. IEEE, (1994)Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC., , , and . ISCAS, IEEE, (2006)Priority depth fusion for the 2D to 3D conversion system., , , , , and . Three-Dimensional Image Capture and Applications, volume 6805 of SPIE Proceedings, page 680513. SPIE, (2008)Automatic threshold decision of background registration technique for video segmentation., , , and . VCIP, volume 4671 of Proceedings of SPIE, page 552-563. SPIE, (2002)