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A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.

Y. Zhou, Z. Zhou, Y. Wei, Z. Yang, X. Lin, C. Dai, L. Hao, C. Peng, H. Cai, and X. Wu. IEEE Trans. Circuits Syst. I Regul. Pap., 71 (1): 187-200 (January 2024)

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Yongliang Huang

Zhou Zhou

Zhou Zhao

Jun Zhou

Other publications of authors with the same name

Writing-only in-MRAM computing paradigm for ultra-low power applications.B. Liu, M. Liu, Y. Zhou, X. Hong, H. Cai, and L. de Barros Naviner. Microprocess. Microsystems, (April 2022)A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators.Y. Zhou, Z. Cheng, H. Liu, T. Xiong, and B. Wang. APCCAS, page 501-504. IEEE, (2022)Magnetic Tunnel Junction Applications.N. Maciel, E. Marques, L. Naviner, Y. Zhou, and H. Cai. Sensors, 20 (1): 121 (2020)MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.Y. Zhou, H. Cai, B. Liu, W. Zhao, and J. Yang. IEEE Trans. Circuits Syst., 67-II (12): 3352-3356 (2020)Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.L. Hao, Y. Wang, Y. Liu, S. Zhao, X. Zhang, Y. Li, W. Lu, C. Peng, Q. Zhao, Y. Zhou and 3 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 32 (5): 883-896 (May 2024)Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices.X. Si, Y. Zhou, J. Yang, and M. Chang. ASICON, page 1-4. IEEE, (2021)A survey of in-spin transfer torque MRAM computing.H. Cai, B. Liu, J. Chen, L. Naviner, Y. Zhou, Z. Wang, and J. Yang. Sci. China Inf. Sci., (2021)A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations.S. Shen, H. Xu, Y. Zhou, and W. Yu. IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 1139-1143 (March 2023)Analysis of how to use the GEB developing.N. Wei, and Y. Zhou. ICEE, page 3723-3725. IEEE Computer Society, (2010)Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices.T. Xiong, Y. Zhou, Y. Kong, B. Wang, A. Guo, Y. Wang, C. Xue, H. Hsu, X. Si, and J. Yang. ISOCC, page 195-196. IEEE, (2021)

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Disambiguation of "Zhou, Yongliang"

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A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.

Please choose a person to relate this publication to

Yongliang Huang

Zhou Zhou

Zhou Zhou

Zhou Zhao

Jun Zhou

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zhou, Yongliang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.

Please choose a person to relate this publication to

Yongliang Huang

Zhou Zhou

Zhou Zhou

Zhou Zhao

Jun Zhou

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.