Author of the publication

An Optimized Compression Strategy for Compressor-Based Approximate Multiplier.

, , , , , , and . ISCAS, page 1-5. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Memory-reduced MAP decoding for double-binary convolutional Turbo code., , and . ISCAS, page 469-472. IEEE, (2010)Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes., and . ISCAS (6), page 5786-5789. IEEE, (2005)FACCU: Enable Fast Accumulation for High-Speed DSP Systems., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (12): 4634-4638 (2022)Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1708-1714 (March 2024)Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm., , and . CoRR, (2019)An Adaptive Chase-Pyndiah Algorithm for Turbo Product Codes., , , and . IEEE Commun. Lett., 27 (4): 1065-1069 (April 2023)A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator., , and . IEEE Trans. Circuits Syst., 67-I (10): 3484-3497 (2020)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)A lightweight face detector by integrating the convolutional neural network with the image pyramid., , , and . Pattern Recognit. Lett., (2020)A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA., , , and . ISVLSI, page 144-149. IEEE, (2021)