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Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's.

, , , , and . ISCAS, page 833-836. IEEE, (1995)

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Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits., , , and . VLSI-DAT, page 1-4. IEEE, (2013)Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process., and . VLSI-DAT, page 1-4. IEEE, (2013)New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process., and . VLSI-DAT, page 1-4. IEEE, (2012)Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology., and . SoCC, page 33-36. IEEE, (2013)Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits., and . ISCAS (1), page 297-300. IEEE, (2003)Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications., and . MWSCAS, page 1-4. IEEE, (2018)Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS., and . CICC, page 689-696. IEEE, (2009)Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices., and . CICC, page 539-542. IEEE, (2009)Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard., and . Microelectron. Reliab., 41 (3): 417-429 (2001)New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance., and . IEEE Trans. Ind. Electron., 57 (10): 3533-3543 (2010)