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Disambiguation of "Sansaloni, T."

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Design of an efficient digital down-converter for a SDR-based DVB-S receiver.

, , , , and . ECCTD, page 256-259. IEEE, (2007)

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T Peters

T Frieberg

T Masselink

T Hohlfeld

T Iwanicki

 

Other publications of authors with the same name

Design of high performance timing recovery loops for communication applications., , , and . SiPS, page 1-4. IEEE, (2006)Design of an efficient digital down-converter for a SDR-based DVB-S receiver., , , , and . ECCTD, page 256-259. IEEE, (2007)Distributed arithmetic radix-2 butterflies for FPGA., , and . ICECS, page 521-524. IEEE, (2001)Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems., , , , and . J. Signal Process. Syst., 56 (1): 35-40 (2009)FPGA-based radix-4 butterflies for HIPERLAN/2., , and . ISCAS (3), page 277-280. IEEE, (2002)A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation., , , , and . ICECS, page 241-244. IEEE, (1999)FPGA based on-line complex-number multipliers., , and . ICECS, page 1481-1484. IEEE, (2001)Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates., , , and . FPL, page 535-538. IEEE, (2005)Digit-Serial Complex-Number Multipliers on FPGAs., , and . J. VLSI Signal Process., 33 (1-2): 105-115 (2003)