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A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling., , , and . IEEE J. Solid State Circuits, 41 (2): 461-473 (2006)Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps., , , , , , and . Proc. IEEE, 98 (12): 1993-2004 (2010)The design of a high-performance scalable architecture for image processing applications., , , and . ASAP, page 722-733. IEEE, (1990)Accurate delay model and experimental verification for current/voltage mode on-chip interconnects., , and . ISCAS (5), page 169-172. IEEE, (2003)P3A: a partitionable parallel/pipeline architecture for real-time image processing., , , , and . ICPR (2), page 529-531. IEEE, (1990)A semiconductor industry perspective on future directions in ECE education., , and . IEEE Trans. Educ., 46 (4): 463-466 (2003)Device and Architecture Outlook for Beyond CMOS Switches., , , , and . Proc. IEEE, 98 (12): 2169-2184 (2010)A perspective on CMOS technology trends., and . Proc. IEEE, 74 (12): 1646-1668 (1986)Limits to binary logic switch scaling - a gedanken model., , , and . Proc. IEEE, 91 (11): 1934-1939 (2003)Introduction to the SRC design sciences program.. DAC, page 216-217. ACM/IEEE, (1984)