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Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.

, , , , , , , and . IEEE Trans. Computers, 63 (6): 1446-1459 (2014)

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Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors., , , , , , , and . IEEE Trans. Computers, 63 (6): 1446-1459 (2014)COMET: A Cross-Layer Optimized Optical Phase Change Main Memory Architecture., , , , and . CoRR, (2023)Modeling Silicon-Photonic Neural Networks under Uncertainties., , and . CoRR, (2020)A NoC Traffic Suite Based on Real Applications., , , , , , , and . ISVLSI, page 66-71. IEEE Computer Society, (2011)CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks., , , and . OFC, page 1-3. IEEE, (2022)Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators., , , and . VTS, page 1-4. IEEE, (2024)OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing., , , , , , and . CoRR, (2023)ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication., , and . ICCAD, page 24:1-24:9. ACM, (2022)Design Space Exploration for PCM-based Photonic Memory., , , and . ACM Great Lakes Symposium on VLSI, page 533-538. ACM, (2023)TRON: Transformer Neural Network Acceleration with Non-Coherent Silicon Photonics., , , and . ACM Great Lakes Symposium on VLSI, page 15-21. ACM, (2023)