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CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks., , , and . OFC, page 1-3. IEEE, (2022)Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors., , , , , , , and . IEEE Trans. Computers, 63 (6): 1446-1459 (2014)COMET: A Cross-Layer Optimized Optical Phase Change Main Memory Architecture., , , , and . CoRR, (2023)Modeling Silicon-Photonic Neural Networks under Uncertainties., , and . CoRR, (2020)A NoC Traffic Suite Based on Real Applications., , , , , , , and . ISVLSI, page 66-71. IEEE Computer Society, (2011)Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators., , , and . VTS, page 1-4. IEEE, (2024)Photonic integrated circuits: A study on process variations., , , and . OFC, page 1-3. IEEE, (2016)System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (2): 292-305 (2013)Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing., , , , , , , , and . CoRR, (2024)Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis., , , and . ISVLSI, page 128-133. IEEE, (2022)