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A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.

, , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 58 (10): 2839-2850 (October 2023)

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34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process., , , , , , , , , and 4 other author(s). ISSCC, page 582-584. IEEE, (2024)A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 58 (10): 2839-2850 (October 2023)A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier., , , , , , , , , and 2 other author(s). ISSCC, page 498-499. IEEE, (2023)Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory., , , , , , , , , and 4 other author(s). VLSI Technology and Circuits, page 224-225. IEEE, (2022)An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron., , , , , , , and . ASICON, page 1-4. IEEE, (2019)RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference., , , , , , , , , and . APCCAS, page 497-500. IEEE, (2022)Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing., , , , , , and . ASICON, page 140-143. IEEE, (2017)Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures., , , , , , , , , and 1 other author(s). Microelectron. Reliab., 54 (4): 746-754 (2014)STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 57 (8): 2560-2573 (2022)MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based Computing in Memory Architecture for Edge AI Devices., , , , , , and . AICAS, page 1-4. IEEE, (2021)