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CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks., , , , и . ISLPED, стр. 1-6. IEEE, (2017)PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs., , , , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 5043-5056 (2022)Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (2): 518-529 (2022)Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC., , , , , и . ASP-DAC, стр. 684-689. IEEE, (2022)High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme., , , , , , , и . NVMSA, стр. 1-6. IEEE, (2021)RL Based Network Accelerator Compiler for Joint Compression Hyper-Parameter Search., , , , и . ISCAS, стр. 1-5. IEEE, (2020)A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 238-240. IEEE, (2021)Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead., , , , , , , , , и . DAC, стр. 156:1-156:6. ACM, (2016)Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers., , , , , , , , , и 1 other автор(ы). VLSI Circuits, стр. 33-34. IEEE, (2018)A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler., , , , , , , , , и . A-SSCC, стр. 61-64. IEEE, (2019)