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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization., , , , , , , , , и 2 other автор(ы). IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 440-448 (2022)Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength., , и . ACM Great Lakes Symposium on VLSI, стр. 399-404. ACM, (2020)AES design improvement towards information safety., , , , , , , и . ISCAS, стр. 1706-1709. IEEE, (2016)PDG: A Prefetcher for Dynamic Graph Updating., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1246-1259 (апреля 2024)OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits., , , , и . ICCAD, стр. 1-9. IEEE, (2023)A body-biasing of readout circuit for STT-RAM with improved thermal reliability., , , , , и . ISCAS, стр. 1530-1533. IEEE, (2015)NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs., , , , и . ISCAS, стр. 1-5. IEEE, (2018)Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint., , , , и . J. Comput. Sci. Technol., 33 (5): 966-983 (2018)STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1285-1296 (2017)SIP: Boosting Up Graph Computing by Separating the Irregular Property Data., , и . ACM Great Lakes Symposium on VLSI, стр. 15-20. ACM, (2020)