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A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design., , и . DAC, стр. 446-451. ACM Press, (1999)DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object., , и . MWSCAS, стр. 1-4. IEEE, (2022)Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization., , , , , и . ASP-DAC, стр. 284-290. ACM, (2021)Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons., , , , , , и . IRPS, стр. 1-6. IEEE, (2023)Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate., и . IEICE Trans. Electron., 102-C (4): 296-302 (2019)Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect., , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (4): 724-731 (2007)Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2441-2446 (2010)Measurement and analysis of delay variation due to inductive coupling., , и . CICC, стр. 305-308. IEEE, (2005)Design guideline for resistive termination of on-chip high-speed interconnects., , и . CICC, стр. 613-616. IEEE, (2005)Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits., , , и . CICC, стр. 215-218. IEEE, (2009)