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High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs.

, , , and . ASP-DAC, page 529-534. IEEE Computer Society, (2007)

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An automated design flow for 3D microarchitecture evaluation., , , , , and . ASP-DAC, page 384-389. IEEE, (2006)An FPGA-Based BWT Accelerator for Bzip2 Data Compression., , , and . FCCM, page 96-99. IEEE, (2019)Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU., , , , and . FCCM, page 127-135. IEEE, (2019)TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2423-2427 (July 2023)TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs., , , , and . CoRR, (2023)Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors., , , and . Quantum, (March 2024)HBM Connect: High-Performance HLS Interconnect for FPGA HBM., , , , and . FPGA, page 116-126. ACM, (2021)Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver., , , , , and . FPGA, page 247-258. ACM, (2023)HMLib: Efficient Data Transfer for HLS Using Host Memory., , , , and . FPGA, page 50. ACM, (2023)Extending High-Level Synthesis for Task-Parallel Programs., , , , , and . FCCM, page 204-213. IEEE, (2021)