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TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2423-2427 (July 2023)

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Efficient ID-based Group Key Agreement with Bilinear Maps., , and . Public Key Cryptography, volume 2947 of Lecture Notes in Computer Science, page 130-144. Springer, (2004)In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 12 (1): 4:1-4:20 (2019)Shrink-Wrapped Boundary Face (SWBF) Algorithm for Mesh Reconstruction from Unorganized 3D Points., , and . IEICE Trans. Inf. Syst., 87-D (9): 2283-2285 (2004)FPGA Implementation of EM Algorithm for 3D CT Reconstruction., , and . FCCM, page 157-160. IEEE Computer Society, (2014)HLScope: High-Level Performance Debugging for FPGA Designs., and . FCCM, page 125-128. IEEE Computer Society, (2017)HLScope+, : Fast and accurate performance estimation for FPGA HLS., , , and . ICCAD, page 691-698. IEEE, (2017)Efficient GPU-Based Graph Cuts for Stereo Matching., and . CVPR Workshops, page 642-648. IEEE Computer Society, (2013)Rapid Cycle-Accurate Simulator for High-Level Synthesis., , , and . FPGA, page 178-183. ACM, (2019)FLASH: Fast, Parallel, and Accurate Simulator for HLS., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4828-4841 (2020)Performance Debugging Frameworks for FPGA High-Level Synthesis.. University of California, Los Angeles, USA, (2019)