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Vector-aware register allocation for GPU shader processors., and . CASES, page 99-108. IEEE, (2015)Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores., , , , , , and . J. Signal Process. Syst., 51 (3): 269-288 (2008)Enabling OpenCL Preemptive Multitasking Using Software Checkpointing., and . ICPP Workshops, page 15:1-15:7. ACM, (2018)Compilation for compact power-gating controls., , and . ACM Trans. Design Autom. Electr. Syst., 12 (4): 51 (2007)Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains., , , , , and . J. Supercomput., 42 (2): 201-223 (2007)CLPKM: A checkpoint-based preemptive multitasking framework for OpenCL kernels., and . J. Syst. Archit., (2019)Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs., , , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 9:1-9:34 (2014)Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors., , and . LCPC, volume 2481 of Lecture Notes in Computer Science, page 45-60. Springer, (2002)Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform., , and . ICPP Workshops, page 12:1-12:7. ACM, (2019)Power-Aware Scheduling for Parallel Security Processors with Analytical Models., , , , , and . LCPC, volume 3602 of Lecture Notes in Computer Science, page 470-484. Springer, (2004)