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Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs., , , и . ACM Trans. Design Autom. Electr. Syst., 20 (1): 9:1-9:34 (2014)System-level design space exploration for security processor prototyping in analytical approaches., , и . ASP-DAC, стр. 376-380. ACM Press, (2005)Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains., , , , , и . J. Supercomput., 42 (2): 201-223 (2007)Compilation for compact power-gating controls., , и . ACM Trans. Design Autom. Electr. Syst., 12 (4): 51 (2007)Support Convolution of CNN with Compression Sparse Matrix Multiplication Flow in TVM., , , , , и . ICPP Workshops, стр. 17:1-17:7. ACM, (2021)Some Classes of Extended Meldelsohn Triple Systems and Numbers of Common Blocks., , , и . Ars Comb., (2001)Power-Aware Scheduling for Parallel Security Processors with Analytical Models., , , , , и . LCPC, том 3602 из Lecture Notes in Computer Science, стр. 470-484. Springer, (2004)Configurable SID-based multi-core simulators for embedded system education., , , и . WESE@ESWEEK, стр. 64-70. ACM, (2009)A sink-n-hoist framework for leakage power reduction., , и . EMSOFT, стр. 124-133. ACM, (2005)Power aware SID-based simulator for embedded multicore DSP subsystems., , , , , , , , и . CODES+ISSS, стр. 95-104. ACM, (2010)