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Disambiguation of "Siddamal, Saroja V."

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Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology.

, , , and . VDAT, volume 1066 of Communications in Computer and Information Science, page 126-140. Springer, (2019)

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V Saile

V Geoffroy

V Wittwer

V Ustinov

V Fendrich

 

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Supply Noise and Peak Current Reduction in High-Speed Output Drivers., , and . VLSID, page 127-132. IEEE, (2023)Development of Data Acquisition System using non-invasive Hardware and 3D software for Electric all terrain Vehicle., and . ICACCI, page 1212-1217. IEEE, (2018)High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone., and . VLSID, page 135-138. IEEE, (2021)Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology., , , and . VDAT, volume 1066 of Communications in Computer and Information Science, page 126-140. Springer, (2019)Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator., , and . VDAT, page 1-5. IEEE, (2020)$2 VDD$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability., and . APCCAS, page 97-100. IEEE, (2021)Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology., , and . VLSID, page 353-358. IEEE Computer Society, (2014)Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter., , , , , , , , and . VLSID, page 251-256. IEEE, (2019)Novel Gate Tracking and N-well Control Circuit for $2VDD$ Tolerant I/O Buffer., and . APCCAS, page 93-96. IEEE, (2021)Design of High-Speed Floating Point Multiplier., , and . DELTA, page 285-289. IEEE Computer Society, (2008)