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A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators., , , and . ISCAS, page 1-5. IEEE, (2020)A 40 kS/sCalibration-Free Incremental △Σ ADC Achieving 104 dB DR and 105.7 dB SFDR., , , , and . ESSCIRC, page 401-404. IEEE, (2023)A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI., , , , and . ESSCIRC, page 141-144. IEEE, (2023)A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 57 (11): 3407-3417 (2022)A reconfigurable Continuous-Time ΔΣ-ADC using a digitally programmable gm-C array., , , , and . MWSCAS, page 810-813. IEEE, (2012)Non-Ideal Reset in Incremental Delta-Sigma ADCs., , , and . NewCAS, page 118-122. IEEE, (2024)PVT robust design of wideband CT delta sigma modulators including finite GBW compensation., , and . MWSCAS, page 382-385. IEEE, (2012)Low power quantizer design in CT Delta Sigma modulators., , , , and . ISCAS, page 1990-1993. IEEE, (2013)Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators., , , , and . ISCAS, page 561-565. IEEE, (2022)A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI., , , , and . ISCAS, page 1-5. IEEE, (2024)