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7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications.

, , , , , , , , , , , , and . ISSCC, page 134-135. IEEE, (2016)

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Performance Analysis of Spiking RBM with Measurement-Based Phase Change Memory Model., , , , , , , , , and . ICONIP (5), volume 1143 of Communications in Computer and Information Science, page 591-599. Springer, (2019)7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications., , , , , , , , , and 3 other author(s). ISSCC, page 134-135. IEEE, (2016)Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation., , , , , , , , , and 21 other author(s). IRPS, page 1-6. IEEE, (2021)Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices., , , , , , and . CoRR, (2014)Accurate Weight Mapping in a Multi-Memristive Synaptic Unit., , , , , , , , , and . ISCAS, page 1-5. IEEE, (2021)Reliability benefits of a metallic liner in confined PCM., , , , , , , , , and 4 other author(s). IRPS, page 6. IEEE, (2018)Endurance Evaluation on OTS-PCM Device using Constant Current Stress Scheme., , , , , , , , , and 8 other author(s). IRPS, page 7-1. IEEE, (2022)A Novel Program-verify Free and Low Drift Multilevel Operation on Cross-point OTS-PCM for In-Memory Computing Application., , , , , , , , , and 5 other author(s). IMW, page 1-4. IEEE, (2024)Reliability Challenges with Materials for Analog Computing., , , , , , , , , and 8 other author(s). IRPS, page 1-10. IEEE, (2019)