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Practical Markov Chain and Von Neumann based Post-processing Circuits for True Random Number Generators.

, , , , , and . MWSCAS, page 841-845. IEEE, (2023)

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A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement., , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)Practical Markov Chain and Von Neumann based Post-processing Circuits for True Random Number Generators., , , , , and . MWSCAS, page 841-845. IEEE, (2023)A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance., , , , and . ESSCIRC, page 513-516. IEEE, (2022)A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response., , , , and . CICC, page 1-2. IEEE, (2023)An Inverter-Based True Random Number Generator with 4-bit Von-Neumann Post-Processing Circuit., , , , and . MWSCAS, page 285-288. IEEE, (2020)A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement., , , and . IEEE J. Solid State Circuits, 56 (7): 2193-2204 (2021)36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In., , , , , , , and . ISSCC, page 502-504. IEEE, (2021)A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique., , , , and . A-SSCC, page 161-164. IEEE, (2018)A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in., , and . CICC, page 1-4. IEEE, (2020)